摘要
介绍了用于ASIC设计验证的静态时序分析方法的基本原理,并在此基础上给出了将该方法用于优化和验证可编程逻辑器件的设计实例。
This paper explicates about the principle of static-timing analysis,which is a timing-verification method of ASIC(application specified integrated circuit)design.This method provides productivity and performance gains for ASIC design,furthermore it can give more efficiency of resource usage in massive PLD(programmable logic device)design.A practical example pesentation demonstrated static-timing analysis merit.
出处
《计算机工程与应用》
CSCD
北大核心
2002年第14期115-116,221,共3页
Computer Engineering and Applications
