摘要
随着半导体工艺技术的不断进步,芯片制造中的工艺变量,越来越难以控制。于是,数字电路后端设计对时序分析提出了更多的要求。越来越多的进程、电源电压、温度(PVT)等工艺角(corner)传统的静态时序分析方法(STA)变得越来越难以精确地估计制程变异(variation)对于设计性能的影响。在本文中,将会介绍一种新的基于统计学的时序分析方法:Statistical Static Timing Analysis(SSTA)。通过一组附加的数据:精确的制程变异描述文件、统计学标准的库文件,SSTA有望在未来取代传统的静态时序分析方法,从而更好的驾驭越来越先进的半导体工艺技术,以及千万门级高速芯片的设计要求。
Along with the developing of semiconductor process technology,process variable in chip manufacturing, became hard to handle with.Because of that,the physical design of digital circuits takes more requirements about the timing analysis. More and more Process,Voltage,PVT,Corners makes traditional STA hard to estimate the influence caused by process variation.In this paper,Wil introduce a new analysis method：Statistical Static Timing Analysis （SSTA）, through a set of additional data：Precise description file of process variation,statistical lib file,SSTA is expected to replace the traditional static timing analysis,In order to take better control of more and more advanced semiconductor technology method,And the requirements of don door level of high-speed chip design requirements.
出处
《数字技术与应用》
2013年第12期64-66,共3页
Digital Technology & Application
关键词
数字后端
统计学
静态时序分析
Physical Design
Statistics
Static Timing Analysis
