摘要
作为分析和验证电路时序行为的重要手段,静态时序分析(STA)技术在深亚微米级ASIC设计中得到了广泛的应用,而正确的时序约束输入是时序分析工具给出正确结果的必要条件之一。文中在介绍STA原理的基础上,以一款H.264/AVC解码芯片为例,分析了解码芯片的时钟结构等时序信息,详细介绍了时钟定义、端口信号等关键时序约束,并重点介绍了PLL时钟偏差的约束设计。时序分析工具PT分析及与动态仿真的交叉验证的结果表明,解码芯片时序约束设计完整、正确。
As an important method of timing analysis and check,Static Timing Analysis （ STA） has been used more and more widely in Nano-scale process. A proper constraint is a necessary condition of precise STA report to be given. In this paper,based on introducing the basic principle of STA,analyze the timing structure and other temporal information of decoder,a critical timing constraints are introduced in detail with the H. 264/AVC as the instance,such as clock definition and port signal,and the clock latency of PLL is stressed. The result of PT and cross-verification with post-sim shows that the constraint design is integrated and correct.
出处
《计算机技术与发展》
2014年第5期90-94,共5页
Computer Technology and Development
基金
"十二五"微电子预研(51308010601)
中国航空工业集团创新基金(2010BD63111)
