摘要
文章简要描述了静态时序分析的原理,并在一款音频处理SoC芯片的验证过程中,详细介绍了针对时钟定义、多时钟域、端口信号等关键问题的时序约束策略。实践结果表明,静态时序分析很好地满足了该芯片的验证要求,而且比传统的动态验证效率更高。
This paper presents the principle of Static Timing Analysis, and presents a case study of the timing constraint strategies applying to an audi SoC （system on chip）. These strategies are used to resolve clock definition, multi-clock domain and other critical problems. The result shows that timing requirements have been well met by STA, which is more effective than dynamic verification method.
出处
《微电子学与计算机》
CSCD
北大核心
2006年第4期64-67,共4页
Microelectronics & Computer
关键词
SOC设计
静态时序分析
静态验证
时序约束
SoC design, Static timing analysis, Static verification, Timing constraint
