摘要
讨论了静态时序分析算法及其在IC设计中的应用。首先,文章讨论了静态时序分析中的伪路径问题以及路径敏化算法,分析了影响逻辑门和互连线延时的因素。最后通过一个完整的IC设计流程介绍了静态时序分析的应用。
This paper addresses static timing analysis and its application in integrate circuits design. Firstly, false paths in static timing analysis and the algorithm to sensitize paths are presented, and then some factors affecting gates and interconnects delay are discussed. Finally, a whole integrate circuits design flow is introduced to emphasize the application of static timing analysis.
出处
《电子器件》
EI
CAS
2006年第4期1329-1333,共5页
Chinese Journal of Electron Devices
关键词
静态时序分析
敏化路径
伪路径
D-算法
static timing analysis
sensitize paths false paths D-algorithm
