摘要
研究雷达机内自测试BIT（builtintest）的实现及雷达系统级测试．依据结构可测性设计方法，采用可编程逻辑器件设计电路板级测试单元，把芯片级边界扫描扩展到雷达系统级测试，并将该方法应用到雷达信号处理机中．给出了板级边界扫描结构和系统级测试的组成结构．雷达信号处理机系统级检测结果表明提出边界扫描测试在系统级应用是可行的．雷达系统级测试的边界扫描方法设计简单，所需硬件少，易于实现，具有在线测试、离线测试以及系统调试等功能，且故障覆盖率高，故障可定位到电路板级和芯片级．
To study the implementation of radar BIT and system level test, the method of boundary scan in chip level was extended to system level by means of BTU and TMU, whlch were deslgned by programmable logic devices. Application of the new method in radar digital signal processor was also given. Testing results in digital signal processor showed the feasibility of the method- With the ability of on line testing, off-line testing and system adjustment, the method is simple for designing and easy to implement because fewer hardwares are needed. In addition, faults can be located to board level and chip level at high fault-coverage-rate.
出处
《北京理工大学学报》
EI
CAS
CSCD
2000年第2期232-235,共4页
Transactions of Beijing Institute of Technology
基金
部级预研项目
关键词
可测性设计
边界扫描
系统级测试
雷达
BIT
design for testability
radar built in test
boundary scan
system level test
