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Radix-16 Booth流水线乘法器的设计 被引量：7

Design of Radix16 Booth Pipeline Multiplier
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摘要 设计了一种新颖的32×32位高速流水线乘法器结构.该结构所采用的新型Radix-16 Booth算法吸取了冗余Booth编码与改进Booth编码的优点,能简单、快速地产生复杂倍数.设计完成的乘法器只产生9个部分积,有效降低了部分积压缩阵列的规模与延时.通过对5级流水线关键路径中压缩阵列和64位超前进位(CLA)加法器的优化设计,减少了乘法器的延时和面积.经现场可编程逻辑器件仿真验证表明,与采用Radix-8 Booth算法的乘法器相比,该乘法器速度提高了11%,硬件资源减少了3%. A novel 32X 32-b high-speed pipeline multiplier structure is designed. Taking advantages of the merits of redundant Booth encoding and modified Booth encoding, the novel Radix-16 Booth algorithm of the structure can simply and quickly generate complicated multiples. The designed multiplier has only 9 partial products, which effectively reduces the size and delay of compression array. By optimizing the compression array and the 64-b CLA （carry-lookahead） adder in the critical path of pipeline, this multiplier can effectively reduce the delay and area, too. The field programmable gate array （FPGA） simulation shows that compared to the multiplier with Radix-8 Booth algorithm, the speed of this multiplier is increased by 11% and its hardware resource is reduced by 3%.
作者 梁峰 邵志标 梁晋
机构地区 西安交通大学电子与信息工程学院 西安交通大学机械工程学院
出处 《西安交通大学学报》 EI CAS CSCD 北大核心 2006年第10期1111-1114,1133,共5页 Journal of Xi'an Jiaotong University
关键词 乘法器 BOOTH算法 流水线 压缩阵列 multiplier Booth algorithm pipeline compression array
分类号 TN47 [电子电信—微电子学与固体电子学]
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参考文献11

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共引文献23

同被引文献42

引证文献7

二级引证文献9

西安交通大学学报
2006年 第10期

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