摘要
针对 Wallace树连接线复杂度高 ,版图实现比较困难的缺点 ,提出了一种新的加法器阵列结构 .这种结构在规则性和连接复杂度方面优于 ZM树和 OS树 .同时提出一种新的 CL A加法器结构以提高乘法器的性能 .乘法器采用 1.5μm CMOS工艺实现 ,完成一次定点与浮点乘法操作的时间分别是 5 6 ns和 76
Wallace tree m ultipliers are very difficult to im plem ent due to their com plex routing requirem ent. A novel tree structure is presented,which requires simpler wiring than ZM trees and OS trees,and a novel CL A adder with30 % faster than the conventional one is proposed too to enhance the speed performance.The multiplier is fabricated with1.5 μm CMOS technology and can perform a32 - bit floating point multiplication ( based on the proposed IEEE P75 4standard format) and a 32 - bit fixed point multiplication in5 6 ns and76 ns,respectively.
