摘要
可测性设计与调试结构设计一般是分别进行的,所需额外硬件资源都较大;然而,它们都是基于扫描技术而展开的,类似的设计结构对硬件资源是很大的浪费。整合测试逻辑和调试逻辑可以很好地降低故障测试和调试在硬件设计和验证等方面的开销,节约设计制造成本。本文将介绍一种故障测试与追踪调试一体化结构,它在保证接近100%故障覆盖率的前提下,同时提供从JTAG端口观察和置位任一内部寄存器的强大追踪调试能力。
Commonly, testability design and debugging structure are made separately, which need a great deal of additional hardware resources. However, they are all based on the scan technology, and their similar structures are a waste of hardware resources. Integrating the test logic with the debnging logic can reduce the cost of design and verification, and save the manufacturing cost. In this paper, an integrated structure of the two tests is proposed. This structure can supply high fault coverage near 100%, and a strong debugging ability of observing and setting any bit of internal registers through the JTAG ports.
出处
《计算机工程与科学》
CSCD
2006年第8期99-100,110,共3页
Computer Engineering & Science
