摘要
探讨了卷积码 Viterbi译码的 FPGA实现问题。在 Viterbi译码算法中 ,提出了减少路径量度的位数和流水线回索法的幸存路径等方法 ,能有效地减少存储量、降低功耗、提高速度 ,使得 K=7的 Viterbi译码算法可在以单片 FP-GA为主的器件上实现。
The FPGA implementation of Viterbi decoding algorithm for convolutional codes is presented The paper proposes some efficient methods to reduce the number of bits to represent the path metrics and the number of saving paths in the process of track back By using these methods,RAM size needed for saving metrics and paths and the power consumption are decreased, and the decoding speed is increased It is shown that the Viterbi algorithm of K =7 can be implemented with a single FPGA chip
出处
《现代电子技术》
2004年第1期41-43,共3页
Modern Electronics Technique
