摘要
幸存路径存储电路ＳＭＵ是Ｖｉｔｅｒｂｉ译码器硬件实现的三大组成部分之一．本文提出的ＶＬＳＩ实现方法不同于传统的寄存器交换法与回索法．它利用带有清零端的Ｄ触发器作为幸存路径的存储单元，利用篱笆图上的状态转移关系及卷积码的合并特性，在少量组合逻辑门——“与非”门的参与下，回索出最大似然路径，进而获得译码结果．我们称这种方法为寄存器回索法．这种方法连线简单、规则，无需缓冲存储单元，译码延时小．因此适于ＶＬＳＩ的实现．
Survivor memory unit(SMU) is one of the three major units which consists of a Viterbi decoder. A novel VLSI approach for realizing SMU differing from the traditional techniques—register exchange and trace-back--is proposed in this paper. This mew method,called Register-Trace-Back,adopts DFFs with resets as the storage for survivor paths.By making use of the trellis connections of the state transitions and the merging property of the convolutional code,the maximum likelihood decision is obtained directly at the presence of some NAND gates. It's interconnection is simple and regular. It's decoding delay is small. No buffer is required. So it is very suitable for VLSI implementation.
基金
浙江大学CAD&CG国家重点实验室开放课题
