摘要
探讨了卷积码编码及其Viterbi译码算法的FPGA(Field-ProgrammableGateArray)实现,根据编码器的结构,分别采用了有限状态机转换的编码法和基于流水线结构的状态转换译码法,有效地提高了编译码的速度。最后给出了(2,1,2)卷积码的编码及其Viterbi译码算法的实验仿真结果。
FPGA Implementation of Convolutional Code encoding and Viterbi Decoding Algorithm is presented. According to the structure of convolutional code, the conversion method of encoding based on limited state machines, and state conversion method of Viterbi Decoding Algorithm based on pipeline operation, are used to increase the speed of encoding and decoding effectively.Lastly, relevant simulation results of encoding and decoding of （2,1,2） convolutional code are given.
出处
《信息与电子工程》
2005年第3期176-178,223,共4页
information and electronic engineering
关键词
信息处理技术
FPGA实现
有限状态机
卷积码
VITERBI译码
information processing technology
FPGA implementation
limited state machines
convolutionalcode
Viterbi decoding
