摘要
文中给出基于软判决和回溯法的高速Viterbi译码器的设计和实现。该译码器采用新颖的幸存路径存储结构和回溯解码电路结构,幸存路径的存储器使用普通的单口RAM组成,能有效节省芯片面积;回溯解码电路简单、易实现,提高译码的速度。在Alera Stratix FPGA器件上仅用2500个LE的资源实现了(2,1,7)卷积码的译码器,达到100MHz以上的译码速度,该译码器适用于高速数字通信领域如数字电视广播等。
A high-speed and area--efficient Vterbi Decoder is presented in the paper. And a new survivor path structure in- cluding RAM blocks and trace--back decode circuit is proposed. The survivor path memory is consist of 4 single-port RAM blocks, which reduces the chip's area comparing to the dual-port RAM structure; and a simple trace-back decoder circuit is implemented to get high speed. Only 2500 LES are used in the Altera Stratix FPGA device to implement this design, and its speed is up to 100 MHz. The proposed Viterbi Decoder can be introduced to the digital communication systems that need high speed such as DTV or HDTV broadcast.
出处
《电子测量技术》
2005年第3期14-15,共2页
Electronic Measurement Technology
