摘要
介绍了一种适用于可编程逻辑器件、为高速同步数据采集设备提供可靠时钟解决方案的全数字锁相环电路。该电路采用路径延时环形数控振荡器,并具备时钟倍频和同步功能,最高工作频率可达100MHz,同步和频率锁定误差不超过1ns。采用标准硬件描述语言设计,可适用于各种可编程逻辑器件,具有简单灵活、可移植性强、易于控制的特点。
An alldigital phase locked loop for highspeed synchronous data acquisition is presented in this paper A ring oscillator called 'path delay' is used in the proposed architecture The circuit can provide clock frequency multiplication and synchronization The maximum operating frequency is 100 MHz with phase error and period error less than 1 ns The device is designed with standard HDL,so it can be implemented in different PLD's
出处
《微电子学》
CAS
CSCD
北大核心
2003年第4期348-351,共4页
Microelectronics
关键词
锁相环
数控振荡器
数据采集
路径延时
可编程逻辑器件
Phase locked loop
Digital controlled oscillator
Data acquisition
Path delay
Programmable logic device
