摘要
时间触发协议是TTA架构必需的通信协议,用于在要求高可靠性的分布式容错实时系统中电子模块之间的互连;目前作为时间触发通信系统重要组成部分的时间触发控制器主要是采用处理器来实现协议的处理,协议开销比较大;基于FPGA的时间触发协议控制器的设计,采用了具有较好同步能力的编码方式和合理的帧格式,在建立全局时间基准的基础上优化了协议处理状态机,利用FPGA的并行处理能力,降低了协议开销,增加了总线的效率,同时也提高了时钟同步精度和容错能力;仿真结果表明,基于FPGA的时间触发协议控制器具有较好的性能。
The Time--Triggered Protocol is integral communication protocol for time--triggered architectures, designed to support the interconnection of electronic modules of distributed fault tolerant real--time systems with stringent dependability requirement. As one of the important components of time--triggered communication system, TTP controller is mainly implemented by processors to achieve the process of protocol. So the overhead of protocol is relatively large. The design of TTP controller based on FPGA adopts an encoding means with good capability of synchronization and reasonable frame structure, and optimizes the state machine of protocol after establishing a global time base. With the capability of parallel processing of FPGA, the design reduces the overhead of protocol and increases the efficiency of the bus and also improves the clock precision and the capability of fault tolerance. The result of simulation shows that the design of TTP controller based on FPGA has a relatively good performance.
出处
《计算机测量与控制》
CSCD
北大核心
2011年第2期322-325,328,共5页
Computer Measurement &Control
