摘要
文章分析了CMOS逻辑门驱动长互连导线时产生的延迟情况,并给出了驱动的延迟模型。在此基础上提出一种新的考虑RC延迟时高速CMOS逻辑链的设计方法。并使用上述方法设计出一款4Mb SRAM的高速译码电路。仿真表明在大扇出、大负载、长互连线的情形下,电路延迟时间仅有1.85ns。比传统的使用等效电容的优化方法快出0.12ns,电路面积节约30%,并且功耗明显的降低。
The delay for the RC-interconnect of CMOS gates has been analyzed. Based on this analysis and its delay models, this paper presents an improved optimization method that can dramatically decrease its area but without loss of its speed for a CMOS gats chain with RC interconnect.At the end, a decoder for a 4Mb SRAM has been designed by the method. The decoder has an excellent performance that its propagation delay was 1.85ns and it save nearly 30% area than the area by the traditional optimization method which inserted ＂effective capacitance＂ instead of RC-interconnect.
出处
《微电子学与计算机》
CSCD
北大核心
2006年第2期96-99,103,共5页
Microelectronics & Computer
