摘要
介绍了ADSP-TS101S与雷达数字中频接口电路原理及其FPGA实现。采用Cyclone芯片设计系统中FIFO缓存、低压差分(LVDS)转换、时钟倍频、控制译码、时序逻辑电路等电路,很好地解决了传统系统中稳定性差,在线升级难等问题,提高了系统的整体性能。
The working principle of the interface between the ADSP-TS101S and radar DIF and its implementation in FPGA is introduced. The circuit of the FIFO, LVDS conversion, multiple-frequency and control logic within a cyclone chip is realized and the problem in the traditional system with bad system-stability and difficulty of upgrading Isystem is settled. As a result it greatly improves the whole performance.
出处
《成都信息工程学院学报》
2006年第1期18-21,共4页
Journal of Chengdu University of Information Technology
