摘要
由于集成电路制造工艺的不断提高 ,集成电路的设计规模遵循Moore定律持续向前发展 ,并出现了系统级芯片 (SOC)这一新的集成电路设计概念 .同时遇到的困难之一是互连线成为影响电路性能的决定因素 :芯片速度变慢、功耗增大、噪声干扰加剧 .若采用以往基于直角互连结构的基础模型进行互连线性能的优化 ,其能力受到限制 .于是 ,人们试图采用其他互连结构作为突破途径 ,以实现高性能的集成电路 .在这种技术需求与目前工艺支持的背景下 ,从 2 0世纪 90年代初出现的关于非直角互连的零散的、试探性的研究 ,将成为国际上布线领域新的热点研究方向 .文中将针对非直角布线方面以往零散的研究工作进行总结与分析 ,指出了目前需要解决的关键技术 ,并结合自己的研究工作基础提出了可行的技术路线与设想 .
With advance in fabrication technology of integrated circuit (IC),the increment of transistors inside one chip has been following the Moore's Law.We can design a chip with more and more functions,which enables system-on-a-chip (SOC) integration.Meanwhile,we face challenges of SOC.One of them is the interconnect effects,which may cause longer delay and heavier crosstalk.To solve the problem,many interconnect performance optimization algorithms have been proposed.However,when the algorithms are designed based on rectilinear on-chip interconnect architecture,the optimization capability is limited.So,researchers begin to present other on-chip interconnect architectures to obtain better optimization result and higher performance.Non-rectilinear on-chip interconnect architectures become a field of active research.Some studies have been made since 1990's.But,those studies are very scattered and incomplete.In this paper,we intend to survey and analyze them.We concentrate on the fundamental problems and key technologies in non-rectilinear on-chip interconnect architectures.We also discuss the corresponding researches and solutions in this research field.
基金
国家高技术研究发展计划 (批准号 :2 0 0 2AA1Z14 6 0 )
国家自然科学基金 (批准号 :6 0 12 112 0 70 6 )资助项目~~
关键词
布线
λ-几何结构
非直角互连
系统级芯片
集成电路
IC CAD
routing
steiner tree
λ-geometry
non-rectilinear on-chip interconnect
system-on-a-chip
