摘要
时延驱动的Ｓｔｅｉｎｅｒ树构造算法是时延驱动总体布线的基础．本文首先简介了求解最佳Ｓｔｅｉｎｅｒ树的Ｄｒｅｙｆｕｓ－Ｗａｇｎｅｒ算法．随后通过引入Ｓａｋｕｒａｉ时延模型，提出了直接基于Ｓａｋｕｒａｉ模型的提高线网时延性能的时延驱动ＤＷ算法．当集成电路工艺的特征宽度较小时，该算法求得的Ｓｔｅｉｎｅｒ树中关键点的时延值，明显小于ＩＤＷ和ＣＦＤ算法的结果．
Abstract This paper presents a new Timing Driven Steiner Tree algorithm. The
algorithm estimates the delay from source to sink of a net based on the Sakurai Delay Model, and
traverses all available Steiner trees via Dreyfus Wagner Steiner approach. Under sub micron
technology, this algorithm will provide much better solution for the delay of critical vertices of net
compared to IDW and CFD algorithm.
基金
国家"九五"科技攻关
高等学校博士学科点专项科研基金
