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具有高k栅介质层的4H-SiC超结UMOSFET研究

Study of 4H-SiC Superjunction UMOSFET with High-k Gate Dielectrics Layer
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摘要 为了缓解SiC UMOSFET栅底部的电场尖峰问题,优化击穿电压(Breakdown Voltage,BV)和特征导通电阻(Ron,sp)的折中关系,利用Sentaurus TCAD仿真软件研究了一种含高k栅介质层与P型屏蔽区的4H-SiC超结UMOSFET结构(Hk SiC SJ UMOS)。该结构在沟槽底部加入了P型屏蔽层来减小栅电场,采用多次外延生长与高能离子注入的方法引入了上下浓度不同的两段P柱形成超结结构,从而在保持高击穿电压的同时降低了特征导通电阻,此外高k栅介质层的加入可以使电场分布更加均匀,同时增加漂移区表面的电荷量以降低特征导通电阻。仿真结果表明,与传统SiC UMOSFET结构(Conv SiC UMOS)相比,未加入高k介质的SiC超结UMOSFET结构(SiC SJ UMOS)击穿电压提升了23.4%,特征导通电阻下降了14.6%,而加入高k介质层后的结构(Hk SiC SJ UMOS)与传统结构相比击穿电压提高了27.8%,特征导通电阻降低了31.1%,其FoM优值是传统结构的约2.37倍,具有更优良的电学特性。 To alleviate the electric field peak issue at the bottom of the SiC UMOSFET gate and optimize the trade-off between breakdown voltage(BV)and specific on-resistance(Ron,sp),a 4H-SiC superjunction UMOSFET structure incorporating a high-k gate dielectric and P-shielding region(Hk SiC SJ UMOS)was investigated using the Sentaurus TCAD simulation software.In this structure,a P-shielding layer is introduced at the trench bottom to reduce the gate electric field.Through multiple epitaxial growths and high-energy ion implantation,two segments of P-pillars with varying concentrations are formed,creating a superjunction structure that effectively reduces specific on-resistance while maintaining high breakdown voltage.Furthermore,the high-k gate dielectric layer promotes a more uniform electric field distribution and increases surface charge in the drift region,further lowering the specific on-resistance.Simulation results indicate that,compared to conventional SiC UMOSFET structures,the superjunction variant without the high-k dielectric(SiC SJ UMOS)improves breakdown voltage by 23.4%and reduces on-state resistance by 14.6%.The Hk SiC SJ UMOS structure enhances breakdown voltage by 27.8%and lowers on-state resistance by 31.1%.Its figure of merit is approximately 2.37 times higher than that of the conventional structure,demonstrating superior electrical performance.
作者 曹荣 冯全源 CAO Rong;FENG Quanyuan(Institute of Microelectronics,Southwest Jiaotong University,Chengdu 611756,P.R.China)
出处 《微电子学》 北大核心 2025年第3期466-472,共7页 Microelectronics
基金 国家自然科学基金重大项目资助(62090012) 四川省重大科技专项项目(2023ZDZX0016)。
关键词 高k介质 4H-SIC 超结 UMOSFET 击穿电压 high-k dielectric 4H-SiC superjunction UMOSFET breakdown voltage
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