摘要
文中提出了一种具有线性掺杂PN型降场层的槽栅LDMOS器件(LDPN TG-LDMOS),以期获得较高的击穿电压和较低的导通电阻。线性掺杂PN型降场层能够优化器件的表面电场并降低结处的电场峰值,从而提高器件的击穿电压。同时,线性掺杂PN型降场层对N型漂移区的辅助耗尽作用能够提高器件的漂移区掺杂浓度,从而降低导通电阻。仿真结果表明,与常规的槽栅LDMOS相比,具有线性掺杂PN型降场层的槽栅LDMOS器件的击穿电压提高了28%,导通电阻降低了50%。
A trench gate LDMOS with linear doped PN top layer(LDPN TG-LDMOS) is presented to improve the tradeoff between the specific on-resistance(Ron,sp) and breakdown voltage(BV).The linear doped PN top layer can generate a uniform electric field at the middle of the device and reduce the high electric peaks at the ends of the drift region,enhancing the BV.The assistant depletion effect on the linear doped PN top layer increases the doping concentration of the drift region,leading to the reduction of the Ron,sp.The simulation results indicate that compared with the conventional TG-LDMOS,the BV of the with LDPN TG-LDMOS is increased by 28% and the Ron,sp is decreased by 50%.
作者
姚佳飞
张泽平
郭宇锋
杨可萌
张振宇
邓钰
YAO Jiafei;ZHANG Zeping;GUO Yufeng;YANG Kemeng;ZHANG Zhenyu;DENG Yu(College of Electronic and Optical Engineering,Nanjing University of Posts and Telecommunications,Nanjing 210023,China;National and Local Joint Engineering Laboratory of RF Integration and Micro-assembly Technology,Nanjing University of Posts and Telecommunications,Nanjing 210023,China;Bell Honors School,Nanjing University of Posts and Telecommunications,Nanjing 210023,China)
出处
《南京邮电大学学报（自然科学版）》
北大核心
2019年第6期22-27,共6页
Journal of Nanjing University of Posts and Telecommunications：Natural Science Edition
基金
国家自然科学基金青年基金(61704084)
国家自然科学基金(61874059)
射频集成与微组装技术国家地方联合工程实验室开放课题(KFJJ20170302)
江苏省高校自然科学基金(17KJB510042)
电子薄膜与集成器件国家重点实验室开放课题(KFJJ201704)
南京邮电大学引进人才科研启动基金(NY218115)资助项目
关键词
线性掺杂
击穿电压
导通电阻
槽栅
LDMOS
linear dope
breakdown voltage
on-resistance
trench gate
lateral double diffused metal oxide semiconductor(LDMOS)
