摘要
理论上Wallace树结构加法器是乘法器中完成部分积求和的最快的多操作数加法器 ,但其互连复杂难于实现 .针对 32位树型乘法器 ,在分析阵列结构的基础上 ,对部分积重新合理分组 ,并采用延迟平衡的 4 2压缩器电路结构 ,提出一种新的阵列组织结构 .该结构与现有其他结构相比具有AT2 最小的特点 ,比传统的Wallace树结构减少了约 18% ,并且布局规整 ,布线规则 ,易于VLSI实现 .
Wallace trees are the theoretically fastest multi operand adders, which can be used for obtaining the sum of partial products. However, their complex interconnections do not permit practical implementation. This paper proposes a novel architecture for 32 bit tree multipliers. The new grouping of partial products is more rational than others. It adopts the delay banlanced 4 2 compressor. As a result, it offers the smallest AT 2 in present architectures, with the estimated reduction around 18%. In addition, the regular placement and routing facilitate VLSI implementation.
出处
《西安电子科技大学学报》
EI
CAS
CSCD
北大核心
2002年第5期580-583,共4页
Journal of Xidian University
基金
国家部委预研基金资助项目 (4 13 0 80 10 3 3 )
