摘要
以一个8位高速并行乘法累加器的IP设计为例子,介绍了一种设计高速乘法累加器的方法.通过在Wallance树模块中改变部分积压缩方式,使该乘法累加器占用的FPGA资源减少了19.8%,而运算速度提高了9.5%.整个设计用VerilogHDL描述,并在Xilinx公司xc2vp20器件上实现.
A new method is introduced by designing IP cores of 8bit fast multiplier-accumulator.The capacity of the multiplier-accumulator is boosted when some techniques are used in the module of the Wallace's tree.Its structure is expressed in VerilogHDL and implemented in the xc2vp20 produced by Xilinx Inc.The result shows a 19.8% decrease in the FPGA sources and a 9.5% increase in the performance with this new method.
出处
《湖南工程学院学报（自然科学版）》
2004年第3期51-54,共4页
Journal of Hunan Institute of Engineering(Natural Science Edition)
