摘要
介绍了一种可嵌入微控制器的8位乘法器的设计。采用基4 Booth算法产生部分积,用一种改进的压缩阵列结构压缩部分积;同时,采用一种减少符号扩展的技术,优化压缩结构的面积,最终对压缩的数据采用超前进位加法器求和电路得到乘积。整个设计采用Verilog HDL进行结构级描述,基于SMIC 0.18μm标准单元库,由Synopsys的DC进行逻辑综合。结果显示,设计的乘法器电路时间延迟为5.31 ns,系统时钟频率达188 MHz。
Design of an 8-bit multiplier for MCD was presented.In this circuit,partial products were generated by modified radix-4 Booth encoding,and then compressed with a modified compression array structure,which was optimized using sign extension reduction technique,and the final product was obtained with CLA array.The whole design was described in Verilog HDL at structure level,and synthesized based on SIMC＇s 0.18 μm standard cell library using DC of Synopsys.Results of the synthesis showed that the proposed multiplier had a delay of 5.31 ns and a system clock frequency up to 188 MHz.
出处
《微电子学》
CAS
CSCD
北大核心
2010年第6期832-835,共4页
Microelectronics
