摘要
论文分析了Montgomery算法,利用迭代加法之间的并行性提出了一种流水并行工作的硬件模乘结构。该结构具有时钟频率高,模幂运算时间短的优点,适合于RSA的模幂运算,可以极大提高RSA加密运算的效率,同时其体系结构适合于高阶Montgomery算法的实现。FPGA实现的结果表明,512位的高速模乘单元工作频率74.27MHZ;1024位的高速模乘单元工作频率73.94MHZ。模乘单元的面积与位宽成正比,而工作频率基本不变。基于此结构,512位的RSA运算时间为1.78ms,1024位的RSA运算时间为7.08ms。
In this paper,a high frequency,fast modular multiplication unit is proposed.The hardware architecture is based on the Montgomery's algorithm and makes use of the parallelism of add operations.It will improve the efficiency of RSA encryption and decryption.Implementing in FPGA,it achieves high frequency and short clock cycle time for modular exponentiation.This architecture can also be applied to high radix Montgomery's algorithm to reduce clock cycle time rapidly.
出处
《计算机工程与应用》
CSCD
北大核心
2003年第26期48-50,共3页
Computer Engineering and Applications
基金
国家部委预研基金资助
关键词
模乘运算
RSA
进位保留加法器
流水链
WALLACE树
Modular multiplication,RSA,carry-save add,pipelining,Wallace tree,modular exponentiation,montgomery's algorithm
