期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

考虑时间因素的不同基本门故障概率计算 被引量：2

The Calculation of Fault Probability of Different Elementary Gates Considering Time Factor
在线阅读 下载PDF
导出
摘要 在门级电路的可靠性概率评估方法中,基本门的故障概率p一般人为设定或以常数形式出现.考虑到不同基本门的故障概率具有随时间变化的特性并结合其输入导线,本文构建了考虑输入负载的随时间变化的不同基本门的故障概率模型.理论分析与实验结果表明,基于弱链接模型的双峰对数正态分布更适合用来表示输入导线故障概率的时间分布.用本文方法、美国军用标准MIK-HDBK-217及Monte Carlo方法计算了ISCAS85基准电路的可靠度并进行了比较,还通过了行业标准的检验,结果验证了本文所构建模型的合理性. The fault probability of the elementary gate p for the reliability estimation of gate-level circuits had been given based on expert experience or as a constant generally. Considering the time change of properties of fault probability and the input-in- terconnects of different elementary gates, a fault probability model considering input loads and time factor is constructed. Theoretical analysis and experimental results show that the bimodal lognormal distribution based on weak link model is more suitable to describe the time distribution of the input-interconnect fault probability. The reliability values of ISCAS 85 benchmark circuits are calculated and compared by the iterative probability transfer matrix based on the proposed model, the reliability calculation method recommend- ed by MIL-HDBK-217 standard and the reliability simulation method adopted by Monte Carlo. The industrial standard is also used to further test. It shows that the orooosed model is reasonable.
作者 肖杰 江建慧
机构地区 同济大学软件学院
出处 《电子学报》 EI CAS CSCD 北大核心 2013年第4期666-673,共8页 Acta Electronica Sinica
基金 国家自然科学基金(No.60903033) 国家973重点基础研究发展计划(No.2005CB321604)
关键词 时间因素 输入负载 输入导线 CMOS器件 不同基本门的故障概率 time factor input load input-interconnect CMOS device the fault probability of different elementary gates
分类号 TP331 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献14

  • 1王真,江建慧.基于概率转移矩阵的串行电路可靠度计算方法[J].电子学报,2009,37(2):241-247. 被引量：18
  • 2J Xiao,J-H Jiang,X-G Zhu.A method of gate-level circuit re- liability estimation based on iterative FIM model[ A]. Proceed- ing of IEEE 17th Pacific Rim International Symposium on De- pendable Computing [C ]. Los Alamitos: 1EEE Computer Soci- ety, 2011.276 - 277.
  • 3Hall J,nao C, Erin B. Reliability evaluation of logic circuits us- ing probabilistic gate models [ J ]. Microelectron Reliability, 2011,51(2) :468 - 476.
  • 4王真 江建慧.考虑版图级因素的PTM中故障感染率的计算.哈尔滨工业大学学报,2009,41:124-129.
  • 5肖杰,江建慧.结合版图结构信息的基本门电路故障概率估计[J].电子学报,2012,40(2):235-240. 被引量：6
  • 6J-X Fang, S S Sapatnekar. Scalable methods for the analysis and optimization of gate oxide breakdown[ A]. Proceeding of IEEE llth Intemational Symposium on Quality Elecvonic De- sign[ C]. Los Alamitos: IE.EE Computer Society, 2010. 638- 645.
  • 7MHDBK-344A. Military handbook: Environmental stress screening of electronic equipment[ S ].
  • 8Liew B K, Fang P, Hu C M. Circuit reliability simulator for in- terconnect, via, and contact electromigration[ J]. IEEE, Transac- tions on Electronic Devices, 1992,39 ( 11 ) : 2472 - 2479.
  • 9Li B Z, Christiansen C, Gill J, et al. Threshold electrornigration failure time and its statistics for Cu interconnectsl J]. Journal of Applied Physics, 2006,100(114516) : 1 - 10.
  • 10Fischer A H, Abel A, Lepper M, et al. Modeling bimodal elec- tromigration failure distributions[J].Microelectronics Reliabil- ity, 2001,41 (3) :445 - 453.

二级参考文献42

  • 1赵天绪,段旭朝,郝跃.集成电路互连线寿命的工艺缺陷影响分析[J].计算机学报,2006,29(2):227-232. 被引量：7
  • 2郝跃,朱春翔.硅片缺陷粒径分布的分形特征及动力学模型[J].电子学报,1997,25(2):73-75. 被引量：1
  • 3Kim J S, Nicopoulos C, Vijakrishnan N, et al. A probabilistic model for soft-error rate estimation in combinational logic[A]. Proc. of the 1 st Int' l Workshop on Probabilistic Analysis Techniques for Real Time and Embedded Systems, Pisa[C]. New York: Elsevier, 2034.25 - 31.
  • 4Asadi G, Tahoori M B. An analytical approach for soft error rate estimation in digital circuits[ A]. IEEE Int. Symp. on Circuits and Systems, Kobe [ C ]. Hoboken: John Wiley & Sons, 2005.2991 - 2994.
  • 5Krishnaswamy S, Viamontes G F, Markov I L, et al. Accurate reliability evaluation and enhancement via probabilistic transfer matrices[A]. Proc. of the Design, Automation and Test in Europe Conference and Exhibition, Munich[C ]. New York: ACM Society, 2005.282 - 287.
  • 6Parker K P and McCluskey E J. Probabilistic treatment of general combinational networks [J]. IEEE Trans on Computers, 1975,24(6) :668 - 670.
  • 7Parker K P and McCluskey E J. Analysis of logic circuits with faults using input signal probabilities[ J]. IEEE Trans on Computers, 1975,24(5) : 573 - 578.
  • 8Ogus R C. The probability of a correct output from a combinational circuit [ J ]. IEEE Trails on Computers, 1975,24 (5) : 534 - 544.
  • 9Zarandi H R, Miremadi S G, Ejlali A R. Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models[ A]. Proc. of the 18th IEEE Int'l Symp. on Defect and Fault-Tolerance in VLSI Systems, Boston[ C]. Washington De: IEEE Computer Society,2003.485 - 492.
  • 10Leveugle R., Cimonnet:D. ,Ammari A. System-Level Dependability Analysis with RT-Level Fault Injection Accuracy[ A]. 19th IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, Cannes, France, 2004 [ C ]. Los Alamitos, California: IEEE Computer Society,2004.451 - 458.

共引文献20

同被引文献36

  • 1赵天绪,段旭朝,郝跃.基于制造成品率模型的集成电路早期可靠性估计[J].电子学报,2005,33(11):1965-1968. 被引量：6
  • 2Way Kuo, Taeho Kim. An overview of manufacturing yield and reliability modeling for semiconductor products [ J ]. Proceed- ings of the IE, F,E, 1999,87(8) :1329 - 1344.
  • 3Kyungmee O Kim, Way Kuo, Wen Luo. A relation model of gate oxide yield and reliability [ J ]. Microelectronics Reliabili- ty,2004,44(3) :425 - 434.
  • 4Military Handbook. Reliability Prediction of Electronic Equip- ment [M]. MILHDBK-217F, Washington: Department of de- fense, 1991.
  • 5Jie Han, Hao Chen, Erin Boykin, et al. Reliability evaluation of logic circuits using probabilistic gate models [ J ]. Microelec- tronics Reliability, 2011,51 ( 2 ) : 468 - 476.
  • 6Jie Xiao, Jianhui Jiang,Xuguang Zhu, et al.A method of gate- level circuit reliability estimation based on iterative PTM model [ A]. Proceedings of the IEEE 17th Pacific Rim International Symposium on Dependable Computing [ C ]. Los Alamitos: IEEE Computer Society,2011.276- 277.
  • 7Walid Ibrahim,Valeriu Beiu,Azam Beg. GREDA: A fast and more accurate gate reliability EDA tool [ J ]. IF.EE Transac- tions on Computer-Aided Design of Integrated Circuits and Systems,2012,31(4) :509 - 521.
  • 8Thomas S Barnett, Adit D Singh, Victor P Nelson. Extending integrated-circuit yield-models to estimate early-life reliability [ J]. IEEE Transactions on Reliability, 2003, 52 ( 3 ) : 296 - 300.
  • 9Kyungmee O Kim. Relating integrated circuit yield and time- dependent reliability for various defect density distributions[J ]. IEEE Transactions on Reliability, 2006, 55 (2) : 307 - 313.
  • 10Fred Kuper, J Van Der Pol, Eric Ooms, et al. Relation between yield and reliability of integrated circuits: experimental results and application to continuous early failure rate reduction pro- grams [ A ]. Proceedings of IEEE Intemafioo.al Reliability Physics Symposium[ C]. New Jersey: IEEE. Electron Devices Society, 1996.17 - 21.

引证文献2

二级引证文献6

电子学报
2013年 第4期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部