摘要
在门级电路的可靠度估计方法中,基本门故障概率p通常是以经验值或人为设定的方式出现,最近才被建模成栅氧化层的故障概率或基本门的输入导线的故障概率.文中结合广义门电路的版图结构信息,分析了故障的形成机理与作用模式、广义门电路的拓扑结构和可靠度的损失机理,并给出了输入导线与栅氧化层的缺陷随时间的生长模型以及缺陷移除率的计算方法,最后建立了包含老化或早期失效的广义门电路的故障概率p模型.通过理论分析与在ISCAS85基准电路上采用经验公式对预测结果进行了拟合,并运用拟合优度检验的策略验证了文中方法的合理性;还分析了老化因素、缺陷移除率、工艺技术、设计方法等对电路可靠度的影响.
In gate-level circuit reliability estimation methods, the fault probability p of an elementary gate,which was commonly given by expert experience, has been modeled as the fault probability of gate oxide or input-interconnects recently. This paper first analyze the formation mechanism and action patterns of faults, the topological structure of generalized gates, and the mechanism of reliability loss by combining the layout structure information. Then we present the defect growth models of gate oxide and input-interconnects to time and the calculation method of the defect remove rate. Finally we propose the p-model of a generalized gate containing the burn-in or early failure period. The proposed p-model is applied on ISCAS85 benchmark circuits. It shows that the calculation results based on the proposed model is successfully simulated with the empirical formula, which verifies the reasonability of the proposed model. The impacts of burn-in, defect remove rate, process parameters and design parameters on circuit reliability are also analyzed.
出处
《计算机辅助设计与图形学学报》
EI
CSCD
北大核心
2013年第4期564-572,共9页
Journal of Computer-Aided Design & Computer Graphics
基金
国家自然科学基金(60903033)
国家"九七三"重点基础研究发展计划项目(2005CB321604)
关键词
缺陷的生长与移除
广义门电路
版图结构
拓扑结构
故障概率
门级电路的可靠性
growth and remove of defect
generalized gate
layout structure
topological structure
fault probability
gate-level circuit reliability
