摘要
为降低金属或金属硅化物源漏与沟道的肖特基势垒高度以改善肖特基势垒源漏场效应晶体管(SBSD-MOSFET)的开关电流比(Ion/Ioff),采用硅化诱发杂质分凝技术(SIDS)调节NiSi/n-Si肖特基二极管(NiSi/n-Si SJD)的肖特基势垒高度,系统地研究了SIDS工艺条件如杂质注入剂量、注入能量和硅化物形成工艺对肖特基势垒高度调节的影响。实验结果表明,适当增加BF2杂质的注入剂量或能量均能显著提高有效电子势垒高度(φBn,eff),也即降低了有效空穴势垒高度(φBp,eff),从而减小反向偏置漏电流。同时,与传统的一步退火工艺相比,采用两步退火工艺形成NiSi也有利于提高有效电子势垒高度,减小反向漏电流。最后,提出了一种优化的调制肖特基势垒高度的SIDS工艺条件。
It is well known that the Ion/Ioff ratio of Schottky barrier source/drain MOSFETs （SBSD- MOSFET） can be improved significantly by reducing the Schottky barrier height （SBH） at the metallic source/channel interface. The tuning of the SBH of NiSi/n-Si Schottky junction diodes （SJD） using silicidation induced dopant segregation （SIDS） was investigated extensively. The effects of implantion dose, energy and the silicidation conditions on the modulation of SBH were illustrated. The test results show that by increasing either the implantation dose or implantation energy of BF2, an obvious increase in the effective SBH to electrons （φBa,eff） was obtained, indicating the reduction of current at reverse bias and the decrease of the effective SBH to holes （φBa,eff）. Meanwhile, It is revealed that the φBa,eff can be modulated to larger value in two-step annealing process than that in traditional one-step annealing process, and reducing the reverse leakage current. An optimized silicidation induced dopant segregation （SIDS） process for tuning the effective SBH of NiSi/n-Si SJDS was proposed.
出处
《半导体技术》
CAS
CSCD
北大核心
2013年第1期55-59,共5页
Semiconductor Technology
基金
中国科学院微电子器件与集成技术重点实验室课题资助项目
