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多时钟域数据传递的FPGA实现 被引量：6

An Implementation of Communicating Data between Multi-clock Domain Based on FPGA
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摘要 分析了多时钟域数据传递设计中亚稳态的产生以及对整个电路性能和功能的影响,以一款异步并行通信接口芯片的设计为例,详细描述了采用同步器、FIFO实现8位并行数据到16位并行数据的两时钟域异步转换的过程。电路在XilinxISE6.0环境下用Modelsim5.7进行了逻辑仿真,结果表明系统稳定可靠。 The paper analyses the metastability which is caused by communicating data between multi- clock domain and effect of metastability to the circuit. For example, the design of asynchronous parallel communication interface chip is described to make use of synchronizer and FIFO to transfer the data band from 8 bits to 16bits between two clock domain in details. The circuit is simulated on a ModelsimS. 7 with Xilinx ISE6.0 software and good test result has gotten.
作者 鲁玲
机构地区 扬州大学能源与动力工程学院
出处 《现代电子技术》 2007年第21期130-132,共3页 Modern Electronics Technique
关键词 多时钟域 亚稳态 FPGA 异步信号 FIFO multi - clock domain metastability FPGA asynchronous signal FIFO
分类号 TP391.98 [自动化与计算机技术—计算机应用技术]
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参考文献4

二级参考文献12

  • 1[1]Verilog HDL高级数字设计Advanced Digital Design with the Verilog HDL, Section 9.7 "FIFOs and Synchronization across Clock Domains", Michael D.Ciletti,电子工业出版社,Feb.2004.
  • 2[2]http:∥www.deeps.org/Tidbits/meta.html WHAT IS METASTABILITY ? 15 Oct 2001.
  • 3[3]http:∥www-s.ti.com/sc/psheets/sdya006/sdya006.pdf Metastable Response in 5-V Logic Circuits,Eilhard Haseloff, SDYA006, Feb. 1997, Texas Instrument.
  • 4[4]Clifford E. Cummings "Synthesis and Scripting Techniques for designing Multi-Asynchronous Clock Designs", SNUG 2001 (Synopsys Users Group Conference, San Jose, CA, 2001). User Papers, March 2001.
  • 5Clifford E Cummings. Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs. SNUG San Jose,CA Voted Best Paper 3rd Place,2001:2～4,16～23.
  • 6Clifford E Cummings. Simulation and Synthesis Techniques for Asynchronous FIFO Design. Sunburst Design, Inc: 6～7.
  • 7Cliffford E Cumming. Synthesis and Scripting Technique for Designing Multi - Asynchronous Clocks Design.
  • 8William J Dally,John W Poulton. Digital Systems Engineering[M]. Cambridge University Press, 1998.
  • 9Scott Hauck. Asynchronous Design Methodologies: An Overview[J] . Proc of the IEEE, 1995,83(1) :69 - 93.
  • 10Michael D Ciletti. Advanced Digital Design with the Verilog HDL[M]. Prentice Hall, 2003.

共引文献23

同被引文献25

  • 1宋宇鲲,王锐,胡永华,高明伦.使用排队论模型对FIFO深度的研究[J].仪器仪表学报,2006,27(z3):2485-2487. 被引量：10
  • 2武文杰,刘皓,李少谦.基于FPGA的支持切换Bank的SDRAM控制器设计[J].信息技术,2006,30(1):33-36. 被引量：7
  • 3IEEE 802. 11a - 1999(R2003) ,Part 11: Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) Specifications[ S].
  • 4S3C2410X 32 - bit RISC Microprocessor Revision 1.2 [ Z]. Samsung Electronics Co. , Ltd.
  • 5DALLY W J, POULTON J W. Digital systems engineering [M]. Cambridge, UK: Cambridge University. Press, 1998.
  • 6BALCH M. Complete digital design[M]. New York: McGraw-Hill, 2003.
  • 7APPERSON R W. A dual-clock FIFO for the reliable transfer of high-throughput data between unrelated clock domains[D]. California: UC Davis, 2004.
  • 8COCHRAN A J, BAILEY P N, CARR L S. FIFO buffer depth estimation for asynchronous gapped payloads: United States Patent. US, 7227876B 1 [P]. 2007-06-05.
  • 9RHA Kyoungscok, CHOI Kiyoung. Arca-efficient buffer binding based on a novel two-port FIFO structure[C]// Proceedings of the Ninth International Symposium on Hardware/Software Codesign. Copcnhagcm: ACM, 2001: 122-127.
  • 10APPERSON R W, YU Z, MEEUWSEN M J, et al. A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains[J]. IEEE Transactions on Very Large Scale Integration (VLS1) Systems, 2007, 15(10): 1125-1134.

引证文献6

二级引证文献21

现代电子技术
2007年 第21期

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