摘要
针对SDRAM时序控制复杂等设计难点,提出了一种基于现场可编程门阵列(FPGA)设计SDRAM控制器的方法。使用状态机的设计思想,采用Verilog硬件描述语言对时序控制程序进行了设计。通过Modelsim SE 6.0开发平台进行了时序仿真,得到的SDRAM读写仿真波形图时序合理、逻辑正确。
According to the difficulty in complex timing control of SDRAM, a general SDRAM controller is designed using Field Programmable Gate Array （FPGA）. The timing control program is designed by using the design concept of state machine and Verilog hardware description language. By using the simulator of the Modelsim SE 6.0, the simulative waveforms for reading and writing SDRAM are presented with reasonable time sequence and correct logic.
出处
《电子设计工程》
2017年第15期137-140,共4页
Electronic Design Engineering
基金
陕西省教育厅科学研究计划项目(14JK1247)
渭南师范学院特色学科建设项目(14TSXK07)
