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一种低压CMOS衬底驱动共源共栅电流镜 被引量：3

A Low Voltage Bulk-driven CMOS Cascode Current Mirror
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摘要 基于PMOS衬底驱动技术设计了低压PMOS衬底驱动CMOS共源共栅电流镜电路(BDCCM),并讨论分析了其输入阻抗、输出阻抗和频率特性。BDCCM的最低输入压降要求只有0.4V,但是其输入输出线性度和频率带宽要比传统的共源共栅电流镜低,是低频低压CMOS模拟集成电路设计的新型高性能共源共栅电流镜。 Based on the PMOS bulk driven technique, a low voltage CMOS cascade current mirror （BDCCM） is presented, and then the input/output impedance and frequency characteristics are discussed. The minimal input voltage of BDCCM is about 0.4 V. Comparing BDCCM with gate driven cascade current mirror （GDCCM）, the linearity of the input/output characteristics and frequency width of BDCCM are lower. So the BDCCM is a good block for low voltage low frequency CMOS analog integrated circuits.
作者 朱樟明 杨银堂 尹韬
机构地区 西安电子科技大学微电子研究所
出处 《固体电子学研究与进展》 CAS CSCD 北大核心 2006年第4期527-530,共4页 Research & Progress of SSE
基金 国家自然科学基金(60476046) 部委基金(51408010304DZ0140 51408010205DZ0164)
关键词 电流镜 互补金属氧化物半导体 低压 模拟电路 current mirror CMOS low voltage analog circuits
分类号 TN402 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献5

  • 1Zhang Xuguang,EI-Masry Ezz I.A regulated bodydriven CMOS current mirror for low voltage applications[J].IEEE Trans Circuits and Systems-Ⅱ:Express Briefs,2004,51 (10):571-577.
  • 2Yan Shouli,Sanchez-Sinencio Edgar.Low voltage analog circuit design techniques:a tutoria[J].IEICE Trans Analog Integrated Circuits and Systems,2000,E00-A[2]:1-17.
  • 3Rajput S S,Jamuar S S.Low voltage analog circuit design techniques[J].IEEE Circuits and Systems Magazine,2002,2 (1):24-42.
  • 4尹韬,朱樟明,杨银堂,郭磊.衬底驱动MOSFET特性分析及超低压运算放大器设计[J].Journal of Semiconductors,2005,26(1):158-162. 被引量：14
  • 5朱樟明,杨银堂,柴常春,殷和国,张春朋,付永朝,杨冰.一种基于0.35μm CMOS工艺的14位100MSPS DAC设计[J].固体电子学研究与进展,2004,24(2):191-195. 被引量：5

二级参考文献14

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共引文献16

同被引文献18

  • 1吴杰,邱关源.CMOS电流镜及其应用[J].湖南大学学报（自然科学版）,1996,23(1):95-100. 被引量：6
  • 2曾健平,邹韦华,谢海情,田涛,叶英.一种新型高输出阻抗,高电流匹配精度电流镜的设计[J].电子器件,2007,30(1):126-128. 被引量：3
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  • 7Juan M Carrillo, Guido Torelli. 1 V rail-to-rail CMOS OpAmp with improved bulk-driven input stage [J]. IEEE Journal of Solid-state Circuit, 2007, 42 (3) : 508-517.
  • 8Long Di, Hon Xianlong, Dong Sheqin. Optional two- dimension common centroid layout generation for MOS transistors unit-circuit[C]. IEEE International Symposium on Circuits and Systems, IEEE Press, 2005,3 : 2999-3002.
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  • 10Wang Z. Analytical Determination of Output Resistance and DC Matching Errors in MOS Current Mirrors[J]. IEEE Proc. Pt G,1990,137(5) :397 - 404.

引证文献3

二级引证文献2

固体电子学研究与进展
2006年 第4期

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