摘要
分析了高速电流舵型D/A转换器中毛刺产生的原因,提出开关对的栅信号转换速度不一致是产生毛刺的主要原因。基于这一理论,解释了输出的三个现象,进行了三个方面的改进,大幅减小了毛刺和建立时间,改善了动态参数。改进后的电路,在电流源输出为30μA、负载为70Ω时,输出电流毛刺峰值从-4.570μA减小到-1.633μA,电压毛刺面积从5.6 pV.s降到2.3 pV.s;在相同仿真条件下,D/A转换器的SFDR值上升了10 dB。
The reason for glitch in high-speed current-steering digital-to-analog converters is analized. A new theory that different speed of falling and rising control signals is the main cause for glitch is proposed. This theory is used to explain three phenomenons. Improvements are made to reduce glitch and settling time, and enhance dynamic characteristics. After improvements, the peak glitch current is reduced from -4. 570μA to -1. 633 μA, and the area of glitch falls to 2. 3 pV, s from 5.6 pV · s for 30 μA output current and 70Ω load resistance. In the same simulation environment, the spurious free dynamic range (SFDR) of the D/A converter rises to 67 dB from 57 dB.
出处
《微电子学》
CAS
CSCD
北大核心
2006年第2期141-144,共4页
Microelectronics
关键词
电流舵
D/A转换器
毛刺
电流开关
寄生电容
Current-steering
Digital-to-annalog converter
Glitch
Current switch
Stray capacitance