摘要
文中提出了一种新颍的SOC芯片BIST方案。该方案是利用相容技术和折叠技术,将SOC芯片中多个芯核的测试数据整体优化压缩和生成,并且能够实现多个芯核的并行测试,具有很高的压缩率,平均压缩率在94%以上;且结构简单、解压方便、硬件开销低,实验证明是一种非常好的SOC芯片的BIST方案。
Novel BIST scheme for SOC was presented in this paper. The test data of multiple cores was taken as one and optimization compressed and built by using compatible compreession and folding compression. Besides it could test multiple cores at one time. The compressibility is very high about 94%, as well as the structure is simpleness and decompression is convenience and the hardware consumption is low. The experiments show that this scheme is superduper for SOC BIST.
出处
《计算机技术与发展》
2006年第5期214-216,共3页
Computer Technology and Development
基金
国家自然科学基金资助项目(#90407008)
教育部留学回国人员科研基金资助项目(#2004.527)
安徽省自然科学基金资助项目(#050420103)
