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一种选择折叠计数状态转移的BIST方案 被引量:12

A BIST Scheme Based on Selecting State Transition of Folding Counters
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摘要 提出了一种选择折叠计数状态转移的BIST方案,它是在基于折叠计数器的基础上,采用LFSR编码折叠计数器种子,并通过选定的存储折叠距离来控制确定的测试模式生成,使得产生的测试模式集与原测试集相等·既解决了测试集的压缩,又克服了不同种子所生成的测试模式之间的重叠、冗余·实验结果证明,建议的方案不仅具有较高的测试数据压缩率,而且能够非常有效地减少测试应用时间,平均测试应用时间仅仅是类似方案的4%· In this paper, a BIST scheme based on selecting state transition of folding counters is presented. On the basis of folding counters, LFSR is used to encode the seeds of the folding counters, where folding distances are stored to control deterministic test pattern generation, so that the generated test set is completely equal to the original test set. This scheme solves compression of the deterministic test set as well as overcomes overlapping and redundancy of test patterns produced by the different seeds. Experimental results prove that it not only achieves high test data compression ratio, but efficiently reduces test application time, and the average test application time is only four percent of the same type scheme.
出处 《计算机研究与发展》 EI CSCD 北大核心 2006年第2期343-349,共7页 Journal of Computer Research and Development
基金 国家自然科学基金项目(60444001 90407008) 安徽省自然科学基金项目(050420103) 教育部留学回国人员科研基金项目(527)
关键词 内建自测试 折叠计数器 测试数据压缩 BIST folding counter test data compression
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参考文献11

  • 1M. Abramoviei, M. Breuer, A. Friedman. Digital Systems Testing and Testable Design. New York: Computer Science Press, 1990.
  • 2梁华国,聚贝勒.海伦布昂特,汉斯-耶西姆.冯特利希.一种基于折叠计数器重新播种的确定自测试方案[J].计算机研究与发展,2001,38(8):931-938. 被引量:44
  • 3梁华国,蒋翠云.使用双重种子压缩的混合模式自测试[J].计算机研究与发展,2004,41(1):214-220. 被引量:38
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二级参考文献32

  • 1[1]M Abramovici, M Breuer, A Friedman. Digital Systems Testing and Testable Design. New York: Computer Science Press, 1990
  • 2[2]K-T Chen, C-J Lin. Timing driven test point insertion for full-scan and partial-scan BIST. The IEEE Int'l Test Conf, Washington, D C, 1995
  • 3[3]Y Savaria, M Yousef, B Kaminska .et al.. Automatic test point insertion for pseudo-random testing. The Int'l Symp on Circuits and Systems, 1991. http://ieeexplore.ieee.org/Xplore/DynWel.jsp
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  • 6[6]K Chakrabarty, S Swaminathan. Built-in self testing of high-performance circuits using twisted-ring counters. The 2000 IEEE Int'l Symp on Circuits and Systems, 2000. http://ieeexplore.ieee.org/Xplore/DynWel.jsp
  • 7[7]C Dufaza, G Cambon. LFSR based deterministic and pseudo-random test pattern generator structures. European Test Conference, Munich, 1991
  • 8[8]S Hellebrand, J Rajski, S Tarnick .et al.. Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers. IEEE Trans on Computers, 1995, 44(2): 223~233
  • 9[9]S Hellebrand, B Reeb, S Tarnick .et al.. Pattern generation for a deterministic BIST scheme. IEEE/ACM Int'l Conf on CAD-95, San Jose, CA, 1995
  • 10[10]S Hellebrand, H-J Wunderlich, A Hertwig. Mixed-mode BIST using embedded processors. Journal of Electronic Testing Theory and Applications (JETTA), 1998, 12(1/2): 127~138

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引证文献12

二级引证文献25

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