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数字电路的高层测试技术及其发展 被引量：3

High-Level Testing of Digital VLSI Circuits and Its Developing Trend
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摘要 简要介绍了数字VLSI电路高层测试的概念,主要的高层测试方法,高层测试中所采用的故障模型及其与门级stuck-at故障的对应关系;并展望了高层测试技术的发展趋势。 High-level testing of digital VLSI circuits is briefly reviewed. The most important highqevel test approaches are described. High-level fault models and its mapping with the stuck-at faults are presented. And finally, the developing trend of high-level testing is discussed.
作者 成本茂 王红 邢建辉 杨士元
机构地区 清华大学自动化系
出处 《微电子学》 CAS CSCD 北大核心 2006年第2期187-191,共5页 Microelectronics
基金 国家自然科学基金资助项目(90207016)
关键词 数字电路 VLSI 高层测试 故障模型 可测性设计 测试综合 Digital IC VLSI High-level test Fault model Design for testability （DFT） Test synthesis
分类号 TN407 [电子电信—微电子学与固体电子学]
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参考文献1

二级参考文献8

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共引文献7

同被引文献19

  • 1白玉媛,杨士元,王红.数字电路自动测试生成实用化软件[J].计算机应用研究,2006,23(1):174-176. 被引量：4
  • 2刘观生,葛海通,陈偕雄.门级电路自动测试向量生成技术原理[J].浙江大学学报（理学版）,2006,33(1):52-57. 被引量：4
  • 3谢永乐,陈光.系统芯片的可测性设计与测试[J].微电子学,2006,36(6):749-753. 被引量：3
  • 4Riesgo T, Uceda J, Aldana F, High-level testing for digital VLSI-a survey[A]. Proc Int Conf Industrial Electronics, Control, and Instrumentation[C]. Hawaii, USA. 1993. 1. 402-407.
  • 5M. L. Bushnell, V. D. Agrawal, "Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits", Kluwer Academic Publishers, 2000.
  • 6Jha N K, Gupta S. Testing of digital systems[M]. Cambridge University Press, 2003.
  • 7Kapur R. High level ATPG is important and is on its way[A]. Proc Int Test Conf[C]. Atlantic City, NJ, USA. 1999.
  • 8Corno F, Reorda M S, Squillero G, RT-level ITC's99 benchmarks and first ATPG result[J]. IEEE Design & Test of Computers, 2000, 17(3).
  • 9Andrew Piziali, "Functional Verification Coverage Measurement and Analysis", Kluwer Academic Publishers, 2004.
  • 10MAXWELL P C. Wafer-package test mix for optimal defect detection and test time savings [J]. Design & Test of Computers, 2003, 20(5): 84-89.

引证文献3

二级引证文献1

微电子学
2006年 第2期

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