期刊文献+

深亚微米工艺下芯片的差分静态电流测试分析

A ΔI_(ddq) Test Solution for Deep Sub-micron Device
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摘要 在分析深亚微米工艺下芯片的差分静态电流(ΔIddq)测试原理的基础上,提出了一套深亚微米工艺下芯片的ΔIddq辅助测试解决方案。通过样本芯片,检验了ΔIddq测试方法的有效性;并根据检验结果,提出了Δ归一化的改进技术。经验证,这种优化后的ΔIddq辅助测量技术可有效筛选出功能测试不能覆盖的故障类型,提高了测试覆盖率。 A feasible △Iddq test solution was proposed for a video processor manufactured in deep sub-micron technology. The solution was optimized with normalized method, and validated with 500 device samples. Experimental results show that the △Iddq test method, which could effectively screen out defective devices that could not be found by functional test or other test methods, is a useful supplement to functional test.
出处 《微电子学》 CAS CSCD 北大核心 2008年第5期633-636,共4页 Microelectronics
基金 上海市科委基金资助项目(04QMX1419,075007033)
关键词 差分静态电流测试 深亚微米器件 故障覆盖率 △Iddq test Deep submicron device Fault coverage
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参考文献8

  • 1MAXWELL P C. Wafer-package test mix for optimal defect detection and test time savings [J]. Design & Test of Computers, 2003, 20(5): 84-89.
  • 2GATTIKER A, MALY W. Current signature [C] // Proc 14^th VLSI Test Syrup. Princeton, NJ, USA. 1997: 156-165.
  • 3成本茂,王红,邢建辉,杨士元.数字电路的高层测试技术及其发展[J].微电子学,2006,36(2):187-191. 被引量:3
  • 4THIBEAULT C. On the comparison of △Ⅰddq and Ⅰddq testing [C]//Proc 17^th VLSI Test Symp. Dana Point, CA, USA. 1999: 143-150.
  • 5POWELL T J, PAIR J, St JOHN M, et al. Delta Ⅰddq for testing reliability [C] // Proc 18^th VLSI Test Syrup. Montreal, Que, Canada. 2000: 439-443.
  • 6LEE P, CHEN A, MATHEW D. A speed-dependent approach for delta IDDQ implementation [C]//Defect and Fault Tolerance in VLSI Systems. San Francisco, CA, USA. 2001: 280-286.
  • 7MANHAEVE H. Current testing for nanotechnologies: myths, facts and figures[J]. Design & Test of Computers, 2004, 21(3): 264-264.
  • 8谢永乐,陈光.系统芯片的可测性设计与测试[J].微电子学,2006,36(6):749-753. 被引量:3

二级参考文献35

  • 1Zarrineh K,Chickermane V.System-on-a-chip testability using LSSD scan structures[J].IEEE Des and Test of Comp,2001,18(3):83-97.
  • 2Zorian Y,Marinissen E J,Dey S.Testing embedded-core based system chips[A].IEEE Int Test Conf[C].Washington D C,USA.1998.130-143.
  • 3Whetsel L.An IEEE 1149.1 based test access architecture for ICs with embedded cores[A].Int Test Conf[C].Washington D C,USA,1997.69-78.
  • 4Bhattacharya D.Hierarchical test access architecture for embedded cores in an integrated circuit[A].IEEE Proc 16th VLSI Test Symp[C].Monterey,CA,USA.1998.8-14.
  • 5IEEE Std 1149.1-1990.IEEE Standard Test Access Port and Boundary-Scan Architecture[S].1990.
  • 6IEEE Std 1149.1-2001.IEEE Standard Test Access Port and Boundary-Scan Architecture[S].2001.
  • 7Immaneni V,Raman S.Direct access test scheme-design of block and core cells for embedded ASICs[A].IEEE Int Test Conf[C].Washington D C,USA.1990.488-492.
  • 8Ghosh I,Jha N K,Dey S.A low overhead design for testability and test generation technique for core-based systems-on-a-chip[J].IEEE Trans Comp Aid Des Circ Syst,1999,18(11):1661-1676.
  • 9Marinissen E J,Kuiper K,Wouters C.Testability and test protocol expansion in hierarchical macro testing[A].Euro Test Conf[C].Rotterdam,The Netherlands,1993.28-36.
  • 10Bouwman F,Oostdijk S,Stans R,et al.Macro testability:the results of production device applications[A].IEEE Int Test Conf[C].Baltimore,MD,USA.1992.232-241.

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