A new partial-SOI （PSOI） high voltage device structure called a CI PSOI （charge island PSOI） is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of t...A new partial-SOI （PSOI） high voltage device structure called a CI PSOI （charge island PSOI） is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n＋-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n＋-regions on the interface by the force with ionized donors in the undepleted n＋-regions, and therefore effectively enhance the electric field of the dielectric buried layer （Ei） and increase the breakdown voltage （BV）, thereby alleviating the self-heating effect （SHE） by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and El of the CI PSOI LDMOS increase to 631 V and 584 V/μm from 246 V and 85.8 V/μm for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.展开更多
A new partial SOI （silion-on-insulator） （PSOI） high voltage P-channel LDMOS （lateral double-diffused metal-oxide semiconductor） with an interface hole islands （HI） layer is proposed and its breakdown character...A new partial SOI （silion-on-insulator） （PSOI） high voltage P-channel LDMOS （lateral double-diffused metal-oxide semiconductor） with an interface hole islands （HI） layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field （Er） in the dielectric buried oxide layer （BOX） and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage （BV）. The values of E1 and BV of an HI PSOI with a 2-~m thick SOI layer over a 1-~tm thick buried layer are 580V/~m and -582 V, respectively, compared with 81.5 V/p.m and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect （SHE）. Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.展开更多
介绍了部分耗尽型 SOI MOS 器件浮体状态下的 Kink 效应及对模拟电路的影响。阐述了 4 种常用体接触方式及其他消除部分耗尽型 SOI MOS 器件 Kink 效应的工艺方法,同时给出了部分耗尽型 SOIM O S F E T 工作在浮体状态下时模拟电路...介绍了部分耗尽型 SOI MOS 器件浮体状态下的 Kink 效应及对模拟电路的影响。阐述了 4 种常用体接触方式及其他消除部分耗尽型 SOI MOS 器件 Kink 效应的工艺方法,同时给出了部分耗尽型 SOIM O S F E T 工作在浮体状态下时模拟电路的设计方法。展开更多
文章对部分耗尽0.8μm SOI CMOS工艺源漏电阻产生影响的四个主要因素采用二水平全因子实验设计[1],分析结果表明在注入能量、剂量、束流和硅膜厚度因素中,硅膜厚度显著影响P+源漏电阻,当顶层硅膜厚度充分时,P+源漏电阻工艺窗口大。实验...文章对部分耗尽0.8μm SOI CMOS工艺源漏电阻产生影响的四个主要因素采用二水平全因子实验设计[1],分析结果表明在注入能量、剂量、束流和硅膜厚度因素中,硅膜厚度显著影响P+源漏电阻,当顶层硅膜厚度充分时,P+源漏电阻工艺窗口大。实验指出注入能量未处于合理的范围,导致源漏电阻工艺窗口不足,影响0.8μm SOI工艺成品率。通过实验优化后部分耗尽0.8μm SOI CMOS工艺P+源漏电阻达到小于200Ω/□,工艺能力显著提高到Ppk>2.01水平,充分满足部分耗尽0.8μm SOICMOS工艺P+源漏电阻需求。展开更多
The identification of soy sauce adulteration can avoid fraud, and protect the rights and interests of producers and consumers. Based on two measurement models (1 mm, 10 mm), the visible and near-infrared (Vis-NIR) spe...The identification of soy sauce adulteration can avoid fraud, and protect the rights and interests of producers and consumers. Based on two measurement models (1 mm, 10 mm), the visible and near-infrared (Vis-NIR) spectroscopy combined with standard normal variate-partial least squares-discriminant analysis (SNV-PLS-DA) was used to establish the discriminant analysis models for adulterated and brewed soy sauces. Chubang soy sauce was selected as an identification brand (negative, 70). The adulteration samples (positive, 72) were prepared by mixing Chubang soy sauce and blended soy sauce with different adulteration rates. Among them, the “blended soy sauce” sample was concocted of salt water (NaCl), monosodium glutamate (C<sub>5</sub>H<sub>10</sub>NNaO<sub>5</sub>) and caramel color (C<sub>6</sub>H<sub>8</sub>O<sub>3</sub>). The rigorous calibration-prediction-validation sample design was adopted. For the case of 1 mm, five waveband models (visible, short-NIR, long-NIR, whole NIR and whole scanning regions) were established respectively;in the case of 10 mm, three waveband models (visible, short-NIR and visible-short-NIR regions) for unsaturated absorption were also established respectively. In independent validation, the models of all wavebands in the cases of 1 mm and 10 mm have achieved good discrimination effects. For the case of 1 mm, the visible model achieved the optimal validation effect, the validation recognition-accuracy rate (RAR<sub>V</sub>) was 99.6%;while in the case of 10 mm, both the visible and visible-short-NIR models achieved the optimal validation effect (RAR<sub>V</sub> = 100%). The detection method does not require reagents and is fast and simple, which is easy to promote the application. The results can provide valuable reference for designing small dedicated spectrometers with different measurement modals and different spectral regions.展开更多
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60436030 and 60806025)
文摘A new partial-SOI （PSOI） high voltage device structure called a CI PSOI （charge island PSOI） is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n＋-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n＋-regions on the interface by the force with ionized donors in the undepleted n＋-regions, and therefore effectively enhance the electric field of the dielectric buried layer （Ei） and increase the breakdown voltage （BV）, thereby alleviating the self-heating effect （SHE） by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and El of the CI PSOI LDMOS increase to 631 V and 584 V/μm from 246 V and 85.8 V/μm for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.
基金supported by the National Natural Science Foundation of China (Grant Nos. 60806025 and 60976060)the Funds of the National Laboratory of Analog Integrated Circuit (Grant No. 9140C0903070904)the Youth Teacher Foundation of the University of Electronic Science and Technology of China (Grant No. jx0721)
文摘A new partial SOI （silion-on-insulator） （PSOI） high voltage P-channel LDMOS （lateral double-diffused metal-oxide semiconductor） with an interface hole islands （HI） layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field （Er） in the dielectric buried oxide layer （BOX） and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage （BV）. The values of E1 and BV of an HI PSOI with a 2-~m thick SOI layer over a 1-~tm thick buried layer are 580V/~m and -582 V, respectively, compared with 81.5 V/p.m and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect （SHE）. Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.
基金Project supported by Key Project of National Natural Science Foundation of China（50531060） National Science Found for Distinguished Young Scholars of China（10525211）+2 种基金 National Natural Science Foundation of China（10572124 10472099） Key Project of Scientific and Technological Department of Hunan Province （05FJ2005）, and the Open Project Program of Low Dimensional Materials ＆ Application Technology （Xiangtan University）, Ministry of Education, China （KF0602）.
文摘文章对部分耗尽0.8μm SOI CMOS工艺源漏电阻产生影响的四个主要因素采用二水平全因子实验设计[1],分析结果表明在注入能量、剂量、束流和硅膜厚度因素中,硅膜厚度显著影响P+源漏电阻,当顶层硅膜厚度充分时,P+源漏电阻工艺窗口大。实验指出注入能量未处于合理的范围,导致源漏电阻工艺窗口不足,影响0.8μm SOI工艺成品率。通过实验优化后部分耗尽0.8μm SOI CMOS工艺P+源漏电阻达到小于200Ω/□,工艺能力显著提高到Ppk>2.01水平,充分满足部分耗尽0.8μm SOICMOS工艺P+源漏电阻需求。
文摘The identification of soy sauce adulteration can avoid fraud, and protect the rights and interests of producers and consumers. Based on two measurement models (1 mm, 10 mm), the visible and near-infrared (Vis-NIR) spectroscopy combined with standard normal variate-partial least squares-discriminant analysis (SNV-PLS-DA) was used to establish the discriminant analysis models for adulterated and brewed soy sauces. Chubang soy sauce was selected as an identification brand (negative, 70). The adulteration samples (positive, 72) were prepared by mixing Chubang soy sauce and blended soy sauce with different adulteration rates. Among them, the “blended soy sauce” sample was concocted of salt water (NaCl), monosodium glutamate (C<sub>5</sub>H<sub>10</sub>NNaO<sub>5</sub>) and caramel color (C<sub>6</sub>H<sub>8</sub>O<sub>3</sub>). The rigorous calibration-prediction-validation sample design was adopted. For the case of 1 mm, five waveband models (visible, short-NIR, long-NIR, whole NIR and whole scanning regions) were established respectively;in the case of 10 mm, three waveband models (visible, short-NIR and visible-short-NIR regions) for unsaturated absorption were also established respectively. In independent validation, the models of all wavebands in the cases of 1 mm and 10 mm have achieved good discrimination effects. For the case of 1 mm, the visible model achieved the optimal validation effect, the validation recognition-accuracy rate (RAR<sub>V</sub>) was 99.6%;while in the case of 10 mm, both the visible and visible-short-NIR models achieved the optimal validation effect (RAR<sub>V</sub> = 100%). The detection method does not require reagents and is fast and simple, which is easy to promote the application. The results can provide valuable reference for designing small dedicated spectrometers with different measurement modals and different spectral regions.
