Circuit net list bipartitioning using simulated annealing technique has been proposed in the paper.The method converges asymptotically and probabilistically to global optimization.The circuit net list is partitioned i...Circuit net list bipartitioning using simulated annealing technique has been proposed in the paper.The method converges asymptotically and probabilistically to global optimization.The circuit net list is partitioned into two partitions such that the number of interconnections between the partitions is minimized.The proposed method begins with an innovative clustering technique to obtain a good initial solution.Results obtained show the versatility of the proposed method in solving non polynomial hard problems of circuit net list partitioning and show an improvement over those available in literature.展开更多
A new transient analysis method for the transmission line circuits is presented in this paper. Based on the semidiscretization of the telegraph equations, a discretized time domain companion models for the transmissio...A new transient analysis method for the transmission line circuits is presented in this paper. Based on the semidiscretization of the telegraph equations, a discretized time domain companion models for the transmission lines which can be conveniently implemented in a general circuit simulator such as SPICE is derived. The computation required for the model is linear with time, equivalent to the recursive convolution-based method. The formulations for both single and coupled lossy transmission lines are given. Numerical experiments are carried out to demonstrate the validity of the method.展开更多
随着超大规模集成电路(Very Large Scale Integrated circuits,VLSI)的高速发展和深亚微米工艺及多层布线技术的广泛应用,器件的密度急剧增长、工作频率不断增加,使互连寄生效应成为制约电路延迟、功耗以及可靠性等重要性能的瓶颈之一...随着超大规模集成电路(Very Large Scale Integrated circuits,VLSI)的高速发展和深亚微米工艺及多层布线技术的广泛应用,器件的密度急剧增长、工作频率不断增加,使互连寄生效应成为制约电路延迟、功耗以及可靠性等重要性能的瓶颈之一。快速、精确地提取三维互连寄生电容已成为高性能集成电路设计中的一个关键环节,也是VLSI设计自动化领域一个热点课题。近十年来,间接边界元多极加速电容提取算法取得了重要的进展,但离实现全路径全芯片电容提取的目标还有很长距离。展开更多
This paper describes an efficient improvement of the multipole accelerated boundary element method for 3-D capacitance extraction. The overall relations between the positions of 2-D boundary elements are considered in...This paper describes an efficient improvement of the multipole accelerated boundary element method for 3-D capacitance extraction. The overall relations between the positions of 2-D boundary elements are considered instead of only the relations between the center-points of the elements, and a new method of cube partitioning is introduced. Numerical results are presented to demonstrate that the method is accurate and has nearly linear computational growth as O(n), where n is the number of panels/boundary elements. The proposed method is more accurate and much faster than Fastcap.展开更多
文摘Circuit net list bipartitioning using simulated annealing technique has been proposed in the paper.The method converges asymptotically and probabilistically to global optimization.The circuit net list is partitioned into two partitions such that the number of interconnections between the partitions is minimized.The proposed method begins with an innovative clustering technique to obtain a good initial solution.Results obtained show the versatility of the proposed method in solving non polynomial hard problems of circuit net list partitioning and show an improvement over those available in literature.
文摘A new transient analysis method for the transmission line circuits is presented in this paper. Based on the semidiscretization of the telegraph equations, a discretized time domain companion models for the transmission lines which can be conveniently implemented in a general circuit simulator such as SPICE is derived. The computation required for the model is linear with time, equivalent to the recursive convolution-based method. The formulations for both single and coupled lossy transmission lines are given. Numerical experiments are carried out to demonstrate the validity of the method.
文摘随着超大规模集成电路(Very Large Scale Integrated circuits,VLSI)的高速发展和深亚微米工艺及多层布线技术的广泛应用,器件的密度急剧增长、工作频率不断增加,使互连寄生效应成为制约电路延迟、功耗以及可靠性等重要性能的瓶颈之一。快速、精确地提取三维互连寄生电容已成为高性能集成电路设计中的一个关键环节,也是VLSI设计自动化领域一个热点课题。近十年来,间接边界元多极加速电容提取算法取得了重要的进展,但离实现全路径全芯片电容提取的目标还有很长距离。
文摘This paper describes an efficient improvement of the multipole accelerated boundary element method for 3-D capacitance extraction. The overall relations between the positions of 2-D boundary elements are considered instead of only the relations between the center-points of the elements, and a new method of cube partitioning is introduced. Numerical results are presented to demonstrate that the method is accurate and has nearly linear computational growth as O(n), where n is the number of panels/boundary elements. The proposed method is more accurate and much faster than Fastcap.
