摘要
用数值计算方法详细模拟了室温及低温(77K)下VLSI电路中金属互连线的寄生电容和时间延迟,得到了金属互连线的几何结构对寄生效应的影响。结果表明,互连线宽W同互连线节距P之比为0.5～0.6是获得最小时间延迟的最佳尺寸。模拟还给出了用铜代替铝金属线及用低介电常数电介质(εlow-k=0.5εSiO2)代替SiO2后。
Parasitic capacitance and time delay for the interconnect in VLSI circuits at room temperature and 77 K are numerically simulated. Results show that a W/P , the ratio of metal interconnect line width to interconnect pitch, of 0.5～0.6 is the optimum interconnect geometry to have the minimum time delay. Also, the simulation demonstrates the improvements of the time delay by using Cu and low k dielectric,instead of using traditional interconnect Al and SiO 2, at room and low temperature (77K).
出处
《微电子学》
CAS
CSCD
北大核心
2000年第1期1-4,7,共5页
Microelectronics
关键词
集成电路
互连线
数值模拟
VLSI
VLSI
Interconnection
Parasitic capacitance
Time delay
Numerical simulation
