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24 Gbit/s 0.2μm PHEMT复接器 被引量：2

24 Gbit/s multiplexer using 0.2 μm PHEMT technology
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摘要 本文利用Philips公司OMMIC 0 2 μmGaAsPHEMT工艺 ,设计出 2 4Gbit/s的复接器 .应用源极耦合FET逻辑 (SCFL) ,使逻辑电路能够在 2 4Gbit/s速率上正常工作 .时钟采用二倍频方案 ,解决了多级复接中的高速时钟问题 .改进异或门拓扑结构实现的二倍频器 ,结构简单、实用 ,降低了电路复杂度 .利用源极耦合电容的微分作用 ,加速晶体管开、关转换 ,提高了选择器工作速度 .芯片通过功能测试验证 ,数据速率可达到 2 4Gbit/s. A 24 Gbit/s multiplexer is realized by using OMMIC 0.2 μm pseudomorphic high electron mobility transistor (PHEMT) GaAs technology of Philips. This circuit is designed with source-coupled field effect transistor logic (SCFL) structure. The clock signal is obtained by using a frequency doubler which uses a modified XOR topology, so that the complexity of the system is reduced. The speed of the selector is accelerated by applying a source-coupled capacitor which speeds up the PHEMT switches. The test results of the function verify that this chip can correctly work at 24 Gbit/s.
作者 杨守军 王志功 朱恩 冯军 熊明珍 夏春晓
机构地区 东南大学射频与光电集成电路研究所
出处 《东南大学学报（自然科学版）》 EI CAS CSCD 北大核心 2004年第3期289-292,共4页 Journal of Southeast University：Natural Science Edition
基金 国家高技术研究发展计划 (863计划 )资助项目(2 0 0 1AA3 12 0 60 )
关键词 光通信 复接器 SCFL 倍频器 Electric network topology Field effect transistors Frequency doublers High electron mobility transistors Optical communication Semiconducting gallium arsenide
分类号 TN492 [电子电信—微电子学与固体电子学]
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参考文献5

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同被引文献19

  • 1Cong H I, Logan S M, Loinaz M J, et al. A 10-Gb/s 16:1 nautliplexer and 10-Ghz clock synthesizer in 0.25-1xm SiGe BiCMOS. IEEE Journal of Solid-State Circuits, 2001, 36(12) : 1946-1955.
  • 2Nakasha Y, Suzuki T, Kano H, et al. A 43-Gb/s full- rate-clock 4:1 multiplexer in InP-based HEMT technolo- gy. IEEE Journal of Solid-State Circuits, 2002, 37 (12) : 1703-1709.
  • 3TangX, WangX J, ZhangS Y, et al. A2-Gb/s 16:1 multiplexer in 0. 18μm CMOS. In: Proceedings of the 2008 IEEE International Conference on Microwave and Millimeter Wave Technology, Nanjing, China, 2008. 868-870.
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  • 6Momtaz A, Cao J, Caresosa M, et al. A fully integrated SONET 0C48 transceiver in standard CMOS. IEEE Jour- nal of Solid-Sate Circuits, 2001, 36(12) : 1964-1973.
  • 7Zhang C C, Wang Z G, Shi S, et al. A 20-Gb/s 1:2 de- multiplexer in 0. 18μm CMOS. Journal of Semiconduc- tors, 2009, 30(5): 055007-1-5.
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引证文献2

东南大学学报（自然科学版）
2004年 第3期

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