摘要
介绍了一个用于高速串行通信中的新颖的高速预放大器和采样器.它们负责对接收到的信号进行预放大和采样.其中,预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度.接收采样器采用 SCFL 结构,能够达到很高的工作速度.电路采用0.13μm CMOS 工艺制造,工作电压为1V,接收信号速率最高可达5Gb/s.测试表明,接收预放大器功耗6mW,采样器功耗2mW.接收器输入信号差分峰一峰值150mV 条件下接收误码率小于10^(-12).
A low voltage and low power Pre-amplifier and a sampler implemented in 0. 13 btm CMOS process are described. The power supply voltage is 1V and the maxim input data rate is 5 Gb/s. The pre-amplifier uses a novel architecture, consisting a feed-forward equalizer to cancel ISI. The sampler employs SCFL architecture which can reach very high speed. Measured pre-amplifier power consumption is 6 mW and the sampler＇s is 2 mW. The test results indicate the receiver BER is less than 10^-12 when input signal amplitude is 150 mV differential peak-to-peak.
出处
《南开大学学报（自然科学版）》
CAS
CSCD
北大核心
2008年第1期13-17,共5页
Acta Scientiarum Naturalium Universitatis Nankaiensis
关键词
高速
放大器
均衡
high-speed
amplifier
equalization
