摘要
为实现室内评测通信网对误码损伤的承受能力,根据CCITT有关文件,对误码损伤模拟用得最多的简单Poisson分布和复合Poisson分布模型进行分析。采用适合于工程的查表模拟法提出了一种数字信号误码损伤模拟系统的实现方案,用PC机和FPGA设计并实现了基于此方案的软、硬件电路。该系统在2048kb/s数据速率上可进行两种误码分布的模拟,误码率可以在10-5～10-2量级上任意设定。
To evaluate the capability in digital error impairment fastness of telecommunication network in lab, the digital error impairment models of simplePoisson distribution and compoundPoisson distribution are analyzed in the typically used method in the digital error impairment, simulator according to the relevant documents of CCITT. The implementation scheme of digital error impairment simulator is discussed by a lookup table method, which is specially suitable for engineering application.Based on the scheme, the software and hardware of digital error impairment simulator is designed and implemented by PC and FPGA. It can simulate digital error at the rate of 2048kb/s with two typical digital error distribution, and the error rate can be set from 10-5 to 10-2 at will.
出处
《桂林电子工业学院学报》
2003年第5期1-4,共4页
Journal of Guilin Institute of Electronic Technology
基金
电科院预研项目(编号:B2000213)
