摘要
为了解决叠层芯片在复杂生产环节中很难进行较为完备的在线测试与传统探针测试方法TSV测试损耗高且难以在绑定后阶段进行测试的问题,结合IEEE 1838标准的叠层芯片边界扫描测试结构和IEEE 1149.4标准的混合信号边界扫描测试结构,设计了基于边界扫描技术的叠层芯片连接性测试结构,其主要包含内部测试总线、测试总线接口电路和能实现将TSV与芯片内核隔离的模拟开关矩阵组成的模拟边界扫描通道,数字/模拟双通道可配置的边界扫描单元和一系列适配叠层芯片边界扫描接口结构;并通过FPGA仿真验证表明测试结构在叠层芯片连接性测试方面尤其是对TSV的电学特性测量具有良好的可控性与可观性,为传统TSV电学参数测量方法提供了一种有效的片上测试途径。
It is difficult for stacked chips to conduct comprehensive online testing in complex production processes,and the traditional probe-based testing method TSV has high testing loss and difficulty in post-bonding stage testing.To solve these issues,combined the boundary scan testing structure of stacked chips based on IEEE 1838 standards with mixed signals based on IEEE 1149.4 standards,a connectivity testing structure for stacked chips based on boundary scan technology was designed,which mainly includes an analog boundary scan channel,a digital/analog channel configurable boundary scan unit,and a series of interface structures adaptable to boundary scan of stacked chips,where the analog boundary scan channel consists of an internal test bus,a test bus interface circuit,and an analog switch matrix that isolates the TSV from the chip core.FPGA simulation verification shows that the testing structure has good controllability and observability in the connectivity testing of stacked chips,especially in the electrical characteristic testing of TSV,which provides an on-chip testing method for traditional TSV electrical parameter measurement methods.
作者
黄新
周雨宇
HUANG Xin;ZHOU Yuyu(School of Electronic Engineering and Automation,Guilin University of Electronic Technology,Guilin 541004,China)
出处
《计算机测量与控制》
2026年第2期1-9,共9页
Computer Measurement & Control
基金
广西自动检测技术与仪器重点实验室项目(YQ23102,YQ23210)
广西类脑计算与智能芯片重点实验室开放基金课题(BCIC-23-K7)。
