摘要
设计了一种具有2条复位路径的鉴频鉴相器。分析了鉴频鉴相器的鉴相死区和鉴相盲区形成原因和对锁相环的影响,采用2条复位路径,分别在鉴相范围为[-π,π]和([-2π,-π]、[π,2π])时工作,针对性地解决鉴频鉴相器的死区和盲区问题,同时根据相位噪声机理对电路进行优化设计。该电路基于TSMC 0.18μm RF CMOS工艺设计仿真。电路仿真结果为:在1.8 V电源电压下,鉴相范围为[-2π,2π],最大工作频率为3.08 GHz,工作在200 MHz频率下的功耗为259.89μw,相位噪声为-150.7 dBc/Hz@1 MHz,版图面积为33.3μm×27.9μm。
Phase-frequency detector(PFD)with two reset paths was designed.The formation causes and effects of dead zone and blind zone on the PFD were analyzed.To address these issues,two reset paths were employed,working at the ranges of[−π,π]and([−2π,-π],[π,2π]),respectively,to solve the problems of dead zone and blind zone.The circuit was optimized based on the mechanism of phase noise.The circuit was designed and simulated using TSMC 0.18μm RF CMOS process.The simulation results show that,under a supply voltage of 1.8 V,PFD has a phase detection rang of[−2π,2π],and has a maximum operating frequency of 3.08GHz,consumes 259.89μw at 200 MHz,and has a phase noise of-150.7dBc/Hz@1MHz.The layout area is 33.3μm×27.9μm.
作者
郭才运
杨潇雨
袁军
李佳伟
付晓君
GUO Caiyun;YANG Xiaoyu;YUAN Jun;LI Jiawei;FU Xiaojun(School of Optoelectronic Engineering,Chongqing University of Posts and Telecommunications,Chongqing 400065,P.R.China;National Key Laboratory of Integrated Circuits and Microsystems,Chongqing 401332,P.R.China;The 24th Research Institute of China Electronics Technology Group Corp.,Chongqing 400060,P.R.China)
出处
《微电子学》
北大核心
2025年第2期263-269,共7页
Microelectronics
基金
集成电路与微系统全国重点实验室基金资助项目(2022-JCJQ-LB-049-6)。
关键词
鉴频鉴相器
锁相环
相位噪声
鉴相盲区
鉴相死区
phase frequency detector(PFD)
phase-locked loop(PLL)
phase noise
blind zone
dead zone
