摘要
介绍了一种基于65 nm CMOS工艺的低相位噪声和低功耗电荷泵锁相环频率合成器。为了提升相位噪声性能,压控振荡器采用了对称PMOS型交叉耦合技术。为了减少杂散对噪声的影响,提出了一种四档可调节复位延迟链的鉴频鉴相器,结合低失配电荷泵设计,可降低鉴相死区引起的带内相位噪声。采用吞咽计数器分频器可显著降低高频时钟分频产生的功耗。提出的锁相环(Phase-locked Loop,PLL)工作频率为4.80~5.38 GHz。根据在5 GHz频率下的后仿真结果,VCO和PLL在1 MHz偏频处的相位噪声分别为−115 dBc/Hz和−110 dBc/Hz。整个PLL的总功耗为6.6 mW,面积仅为0.66 mm×0.64 mm。利用CML高速二分频器,提出的低功耗低相噪电荷泵锁相环可为WLAN/Wi-Fi收发器生成2.40 GHz至5.38 GHz的高质量本振时钟。
This paper presents a low-phase-noise,low-power charge pump phase-locked loop(CPPLL)frequency synthesizer based on the 65-nm CMOS process.To improve phase noise performance,a symmetric PMOS cross-coupled topology is employed in the voltage-controlled oscillator(VCO).To mitigate spurious noise,a four-step adjustable reset delay chain is proposed for the phase frequency detector(PFD),combined with a low-mismatch charge pump design to reduce in-band phase noise caused by phase detection dead zones.A swallow counter divider is adopted to significantly reduce power consumption associated with high-frequency clock division.The proposed PLL operates over a frequency range of 4.80-5.38 GHz.Post-simulation results at 5 GHz show that the phase noise of the VCO and PLL at a 1 MHz offset frequency are−115 dBc/Hz and−110 dBc/Hz,respectively.The overall PLL consumes only 6.6 mW of power and occupies an area of 0.66 mm×0.64 mm.By employing a CML high-speed divide-by-two circuit,the proposed CPPLL can generate high-quality local oscillator clocks ranging from 2.40-5.38 GHz for WLAN/Wi-Fi transceivers.
作者
李铁虎
郭超东
张伟
黄锦涛
曾军
张俊安
LI Tiehu;GUO Chaodong;ZHANG Wei;HUANG Jintao;ZENG Jun;ZHANG Jun'an(School of Artificial Intelligence,Chongqing University of Technology,Chongqing 401135,P.R.China)
出处
《微电子学》
北大核心
2025年第3期364-369,共6页
Microelectronics
基金
重庆市教委科学技术研究项目(KJQN202501106)
重庆理工大学研究生教育高质量发展行动计划资助项目(gzltd202403,gzljg2023309,gzlcx20243566,gzlcx20253414)。
关键词
锁相环
可调复位延迟链
鉴频鉴相器
电荷泵
双电感振荡器
phase-locked loop
adjustable reset delay chain
phase frequency detector
charge pump
dual-inductor oscillator
