摘要
随着电子产品向小型化、集成化方向发展,传统的表面贴装电阻器在电路板上的空间占用和成本问题逐渐显现。为了解决这些挑战,本文提出了一种印制电路塞孔技术应用于板级埋置电阻的研究。通过在印制电路板(PCB)孔内填充电阻浆料,实现电阻元件的埋置,避免了传统电阻器的面积占用,进而降低了PCB的整体成本。通过优化浆料的成分和孔洞的尺寸设计,能够确保电阻值的准确性和稳定性。实验结果表明,采用此方法制备的埋置电阻具有良好的电气性能及较高的稳定性,并能够有效减少PCB表面空间的占用,为多层电路板的设计提供了新的解决方案,为PCB行业的高密度互联设计提供了创新思路。
With the trend of miniaturization and integration in electronic products,the space occupation and cost issues associated with traditional surface-mounted resistors on printed circuit boards(PCB)have become increasingly evident.To address these challenges,this paper presents a study on the application of printed circuit board via-filling technology for embedded resistance.The method involves filling the vias in the PCB with resistor paste,enabling the embedding of resistive components and thereby eliminating the space occupation of traditional resistors,which consequently reduces the overall cost of the PCB.By optimizing the composition of the paste and the design of via dimensions,the accuracy and stability of the resistance values are ensured.Experimental results demonstrate that the embedded resistors produced by this method exhibit excellent electrical performance,high stability,and effectively reduce the space occupation on the PCB surface.This approach provides a new solution for multi-layer PCB design and offers an innovative concept for high-density interconnect design in the PCB industry.
作者
王坤
王守绪
周国云
孙炳合
谢开彬
Wang Kun;Wang Shouxu;Zhou Guoyun;Sun Binghe;Xie Kaibin
出处
《印制电路信息》
2025年第S1期59-64,共6页
Printed Circuit Information
基金
“黄海明珠人才计划”项目
关键词
埋置电阻
塞孔技术
高密度互联
Embedded Resistor
Via-Filling Technique
High-Density Interconnect
