摘要
一种高速ＣＭＯＳ比较器，采用二级正反馈结构和一级推挽输出结构，通过优化传输速度和增益，在３μｍ工艺中，模拟表明它的最小分辨率±ＬＳＢ为±４．９ｍＶ，输入动态范围为±２．５Ｖ（±２．５Ｖ电源电压），相应于９位比较精度，而工作频率达３０ＭＨｚ．用单层金属、双层多晶硅ＣＭＯＳ工艺实现，版图面积为２９５μｍ×２６６μｍ，功耗９．７２ｍＷ．
A high speed comparator,which adopts two stage positive feedback and one push pull output stage structure. The simulation results show that after the propagation speed and gain are optimized,±LSB of the comparator is ±4.9 mV,and its input dynamic range is ±2.5 V(±2.5 V supply voltage),which corresponds to 9 bit resolution. Moreover,its operation frequency could be as high as 30 MHz. It is designed in 3 μm single metal double polysilicon CMOS technology. The chip size is 295 μm×266 μm,and the power consumption of the comparator is 9.72 mW.
出处
《复旦学报（自然科学版）》
CAS
CSCD
北大核心
1999年第3期267-271,276,共6页
Journal of Fudan University：Natural Science
基金
国家自然科学基金
