摘要
针对一款嵌入式10位逐次逼近型A/D转换器,我们设计出一种低功耗高精度的比较器。该比较器采用多级结构,其中前三级是带有正反馈的差分放大器,而后三级则是简单的反相器。此外,我们在电路中引入输入失调校准和输出失调校准的混合技术,以及实现自清零的电路技术。该比较器还采用SMIC0.25μmCMOS工艺模型,在2.5V电源电压下,我们使用HSPICE仿真的结果表明:其比较精度可达到0.2mV、速度为20MHz,而功耗仅为8μW。
A low-power, high-resolution comparator is presented for a 10-bit successive approximation analog-to-digital converter. In order to meet the high-resolution, a multi-stage structure consisting of three differential amplifier and three simple inverters, a multistage calibration techniques and auto-zeroed circuit is used in this comparator, which is designed and fabricated in SMIC 0.25μm CMOS technology. Simulation results show that it can distinguish 0.2mV at 20MHz under 2.5V supply voltage, with only 8μW power consumption.
出处
《微计算机信息》
2009年第20期255-257,共3页
Control & Automation
基金
基金申请人:于宗光周云波
项目名称:系统集成芯片(SOC)中IP模块的设计与验证方法研究
颁发部门:江苏省自然科学基金委员会(BK2007026)
关键词
比较器
级联结构
正反馈
失调校准
自清零
Comparator
Multistage structure
Positive feedback
Multistage calibration
Auto-zeroed
