摘要
在分析LDO中频段电源噪声抑制比的基础上,采用自适应偏置结构,设计了一种高电源噪声抑制比的LDO电路。通过进一步引入基于高通滤波器的电源噪声抑制增强电路,提升了LDO在中频段电源噪声抑制比。电路采用0.13μm CMOS工艺设计,整个芯片面积为0.123mm2,静态电流为29.3μA,功率管上电压降为0.2V。LDO的电源噪声抑制比在100kHz时为65dB,在2MHz时可达75dB。
An improved power supply rejection LDO circuit with an adaptive biasing structure was designed based on the analysis of the factors affecting the LDO power supply rejection limits in mid-frequency. A power supply noise rejection enhanced circuit with high-pass filters was introduced to increase the circuit＇s capability for rejecting the power supply noise in mid-frequency. The proposed circuit was designed in a 0.13μm CMOS process, and the entire chip area was 0. 123 mm^2. The quiescent current was 29.3μA, and the power transistor＇s voltage drop was 0.2 V. The circuit＇s PSRR was 65 dB at 100 kHz, and 75 dB at 2 MHz.
出处
《微电子学》
CAS
CSCD
北大核心
2015年第5期590-593,598,共5页
Microelectronics
基金
预研项目(51308020305)
模拟集成电路重点实验室基金资助项目(9140C090503140C09045)
