摘要
设计了一种适用于MPEG_2视频解码的可变字长解码器 (VLD) ,根据数据流的特点进行了模块划分 ,减少硬件开销 ;根据MPEG_2变字长码表的特点 ,采用码字分割 ,减少码字的存储空间 ;采用并行移位器 ,使每个周期能处理一个码字 .采用VERILOG语言进行描述并通过仿真 ,用FPGA硬件实现后实际放映DVD影碟得以验证 .通过Synop sys工具 ,用 0 .2 5μm工艺库综合 ,最坏情况下 (4.75V ,70℃ )的工作时钟频率为15 0MHz ,设计电路规模为五十万门左右 .FPGA工作频率为 5 0MHz .
A novel design of Variable Length Decoder (VLD) for MPEG_2 vedio decoder is proposed in this paper according to the characteristics of MPEG_2 data flow and DCT coefficients table.The parallel method (decoding multiple bits per cycle ) is adopted so one wordcode can be decode per cycle. The architecture was described in VERILOG and simulated. The VLD is synthesized with 0.25 μm library,and is implemented in about five hundred thousands gates when operating at 150 MHz in the worst condition (4.75 V,70 ℃).
出处
《华南理工大学学报（自然科学版）》
EI
CAS
CSCD
北大核心
2001年第12期89-92,共4页
Journal of South China University of Technology(Natural Science Edition)
